Patent Number: 7594150
Inventor(s): Chakraborty; Tapan Jyoti (West Windsor, NJ), Jagirdar; Aditya (Highland Park, NJ), Oliveira; Roystein (Highland Park, NJ)
Date Issued: 9/22/2009
Abstract: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.